fast multiplier
英 [fɑːst ˈmʌltɪplaɪə(r)]
美 [fæst ˈmʌltɪplaɪər]
快速乘法器
双语例句
- Lagrange solution is employed to convert the constrained optimization problem and bisection method is used to reach a fast convergence in searching for the optimize Lagrange multiplier.
该算法利用拉格朗日算法将约束条件下的最优化问题进行转化，并采用对分算法加快搜索最优拉格朗日乘子的收敛速度。 - A Fast Finite Field Multiplier Architecture and Its VLSI Implementation
一种快速有限域乘法器结构及其VLSI实现 - Custom Design of 32-Bit Fast Multiplier
一种32位全定制高速乘法器设计 - A Fast Floating-Point Multiplier Architecture
一种快速的浮点乘法器结构 - A Fast Multiplier for Elliptic Curve Cryptosystems over Composite Fields
一种基于复合域的ECC的快速乘法器 - SVM Fast Training Algorithm Research Based on Multi-Lagrange Multiplier
多拉格朗日乘子协同优化的SVM快速学习算法研究 - IP design of fast multiplier based on PLD
基于可编程逻辑器件的高速乘法器IP设计 - Several improved booth algorithms to realize fast multiplier
实现快速乘法的几种改进贝斯算法 - Reconfigurable and Fast Finite Field Multiplier Architecture
一种可重构的快速有限域乘法结构 - A Fast Multiplier Design and Implication over Finite Fields
一种基于有限域的快速乘法器的设计与实现 - This paper describes the design of a kind of 32 × 32bit fast parallel multiplier, introduces partial product generation circuit based on modified Booth algorithm, Wallace tree and 4 ∶ 2 compressor.
本文描述了一种32×32位快速并行结构乘法器，介绍了基于修正布斯编码算法的部分积产生电路，并对部分积的符号扩展进行了简化。 - A novel Enhanced Multiple-Output Domino Logic ( EMODL)~() and the sizing optimization of its n-MOS ( evaluation) tree are covered in detail in this paper. It is utilized to implement a fast 20 × 20 bit pipelined multiplier with low power consumption.
文中详尽论述了新型的增强型多输出多米诺逻辑（EMODL）及其n-MOS赋值树的尺寸优化方法，并用它实现了高速低功耗20×20bit流水线乘法器。 - Three improved fast multiplier algorithms based on traditional Booth: Fully Redundant Booth, Partially Redundant Booth, Booth with Bias are analysed and evaluated in this thesis.
分析并评价了在传统贝斯算法基础上改进的几种算法，它们分别是完全冗余贝斯算法、局部冗余贝斯算法，以及有偏差的贝斯算法。 - A fast finite field multiplier is proposed in this paper.
提出了一种快速有限域乘法器结构。 - A fast recursive multiplication algorithm is used in the design of 32-bit multiplication operation. And the design goal is achieved. Thirdly, in the design of multiplier module, the more research is on the multiplier.
本设计采用了快速递归乘法算法设计实现了32位乘法的操作，达到了设计目标。乘法模块的设计中重点对乘法器的设计做了深入的研究。 - It becomes attractive how to design a fast, simple and regular multiplier.
如何设计出高速、简单且结构规则的浮点乘法器成为广泛关注的问题。